1. Field of the Invention
The present invention relates generally to computer systems, and in particular, to peripheral and memory devices which can communicate with a computer system's chip-set by switching between an Industry Standard Architecture (ISA) bus and a Low Pin Count (LPC) bus.
2. Background Art
Conventional legacy-based computer systems include a variety of peripheral and memory devices that communicate with the system's chip-set or processor via an Industry Standard Architecture (ISA) bus or an Expansion bus (X-bus). The system chip-set must include a large amount of pins (e.g., approximately 50-70 pins) and associated circuitry to support the ISA bus or X-bus signals that are used to interface the chip-set or processor with legacy-based peripheral devices, including input/output (I/O) or I/O controller devices such as parallel port controllers, serial port controllers, super I/O controllers, floppy disk controllers, keyboard controllers, and memory devices such as non-volatile memory devices that store, for example, basic input-output services (BIOS) information.
The large number of pins needed to support the ISA bus and X-bus standards generally increases overall system cost. As a result, U.S. Pat. No. 6,131,127 to Gafken et al. discloses a Low Pin Count (LPC) bus that is capable of replacing the ISA bus or X-bus in a computer system. The LPC bus would be capable of supporting the same type of peripheral and memory devices, but utilizes a relatively smaller number of pins or signal lines (e.g., approximately 6-8 signal lines). The LPC bus provides a communication mechanism between a host (such as a processor or chip-set) and peripheral devices (such as I/O or I/O controller devices) or memory devices. The signal lines on the LPC bus are capable of carrying time-multiplexed address, data and control information to implement memory, I/O, direct memory access (DMA), and master bus transactions between the host and the peripheral or memory devices.
With the advent of the LPC bus, there is now available a new standard for communications between a host and a peripheral device. Since peripheral devices are often manufactured by different companies without knowing the intended bus on which the peripheral or memory device will be used, there still remains a need for peripheral and memory devices that are capable of being used with either the ISA bus or the LPC bus.